Design of five-stage pipelined risc-v processor for embedded scenarios

Yu Anning1,2
Huang Han1,2
Li Jie1,2
Zeng Xiaoping3
1. School of Computer Science and Engineering (School of Artificial Intelligence), Chongqing University of Science and Technology, Chongqing· 401331, China
2. Chongqing Key Laboratory of Intelligent Connected Vehicle Collaboration and Safety, Chongqing· 401331, China
3. School of Microelectronics and Communication Engineering, Chongqing University, Chongqing· 400065, China

Abstract

To meet the demands of distributed control nodes in intelligent connected vehicles and Internet of Things (IoT) applications for low cost, low power consumption, and high real-time performance, this paper designed and implemented a 32-bit five-stage pipelined processor core based on the RISC-V RV32IM instruction set. The processor adopted a five-stage pipeline architecture and integrated a hardware multiply-divide unit. It introduced dynamic branch prediction and data forwarding techniques to suppress pipeline stalls caused by control hazards and data hazards, thus improving instruction execution efficiency per unit frequency. The design implemented the processor in Verilog HDL and constructed a System-on-Chip (SoC) over the AXI4-Lite bus. Differential testing completed the logical functional verification. Comprehensive evaluation on the Xilinx KU5P FPGA platform shows that the processor consumes only 5, 712 Slice LUTs and 2, 091 registers at 200 MHz. It achieves 1.62 DMIPS/MHz and 2.81 CoreMark/MHz. Compared with Hummingbird E203, DMIPS and CoreMark performance improve by 30.6% and 31.3%, respectively. Compared with VexRiscv, the improvements reach 30.6% and 19.6%, respectively. Results demonstrate that this architecture maintains an extremely low hardware resource footprint while significantly enhancing computational efficiency. It provides a RISC-V processor solution that balances high performance and high energy efficiency for resource-constrained embedded applications.

Foundation Support

重庆市自然科学基金创新发展联合基金(市教委)项目(CSTB2025NSCQ-LZX0120)
重庆市教委科学技术研究项目(KJQN202501524)
重庆科技大学本科教育教学改革研究项目(202553)
全国高等院校计算机基础教育研究会计算机基础教育教学研究课题(2025-AFCEC-769)

Publish Information

DOI: 10.19734/j.issn.1001-3695.2026.02.0028
Publish at: Application Research of Computers Accepted Paper, Vol. 43, 2026 No. 9

Publish History

[2026-05-26] Accepted Paper

Cite This Article

于安宁, 黄晗, 利节, 等. 一种面向嵌入式场景的五级流水线RISC-V处理器设计 [J]. 计算机应用研究, 2026, 43 (9). (2026-06-02). https://doi.org/10.19734/j.issn.1001-3695.2026.02.0028. (Yu Anning, Huang Han, Li Jie, et al. Design of five-stage pipelined risc-v processor for embedded scenarios [J]. Application Research of Computers, 2026, 43 (9). (2026-06-02). https://doi.org/10.19734/j.issn.1001-3695.2026.02.0028. )

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  • Application Research of Computers Monthly Journal
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Application Research of Computers, founded in 1984, is an academic journal of computing technology sponsored by Sichuan Institute of Computer Sciences under the Science and Technology Department of Sichuan Province.

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